1. Field of the Invention
The present invention relates to the production of circuitized layers and multi-layer ceramic laminates for electronic applications, and more particularly to the production of laminates from a plurality of dielectric ceramic greensheets and interposed patterned conductive circuit layers interconnected by conductive vias to form multilayer sub-laminate units which can be combined or stacked and sintered to form multilayer ceramic (MLC) composition packages comprising a large number of interconnected printed circuit layers for complex electronic applications.
The increasing demands for miniaturization and greater electrical capacity of electronic components has created production and performance problems. For example, miniaturization requires the use of thinner insulating ceramic greensheet layers, finer-line printed circuit conductive layers and smaller, more precise vias or bores through each greensheet layer to receive conductive paste and connect predetermined fine-line circuitry of the patterned conductive layers spaced by the insulating greensheet layers.
Thin greensheet layers, less than about 3 mils in thickness, are difficult to process into multi-layer ceramic laminates in the conventional production process because the thin greensheets distort greatly during normal processing, particularly during screening/post drying, and distorted or warped greensheets cannot be laminated into electrically-continuous packages.
A fine line printed circuit technology is also important because it provides extendibility of MLC technology beyond thick film screened lines and mechanically punched vias. With the current MLC production techniques of screening and punching, feature sizes are typically limited to a minimum line width of about 75 .mu.m, a minimum via diameter of 100 .mu.m, and a via grid of 275 .mu.. center to center. A method for routinely making submicron width lines, and vias with diameters as small as 50 .mu.m on a 125 .mu.m grid, is desirable. Finer lines and via grids will enable reduction of the number of layers with line traces, and a smaller via grid will enable direct joining of the chip C4 footprint to the vias. Both interchip wiring capability and power supply capability to chips will be enhanced. Module costs can be reduced by reducing the number of thin film wiring layers, and in some applications eliminating the use of thin film wiring layers. Thinner substrate and smaller module size are also important for those applications where the module is subject to size and weight constraints. In addition, eliminating the need for screening masks would reduce product development time, enhance flexibility of the package design, and, coupled with a low dielectric constant ceramic composite, such as a cordierite-silica mixture, would provide performance approaching that of polymer thin films.